In the technical field of PLL circuits, a fractional PLL circuit that has a rational number frequency division ratio is known (for example, see Japanese Patent Application Publication Number 2007-288375).
FIG. 12 is a block diagram illustrating a constitution of a fractional PLL circuit according to a conventional technique. To a phase frequency comparator 1, an input clock signal comp_ck that is generated by a reference clock generator (not illustrated) and becomes a reference signal, and a feedback signal fb_ck are inputted. The phase frequency comparator 1 detects a phase difference between the two inputted signals and outputs it to a charge pump 2. The charge pump 2 outputs a charge pump voltage that is increased or decreased in accordance with the phase difference to a loop filter 3. The loop filter 3 outputs a control voltage based on the charge pump voltage to a voltage-controlled oscillator (VCO) 4.
The voltage-controlled oscillator 4 generates an output clock signal vco_ck that has a frequency and a phase based on the control voltage, and outputs it. The output clock signal vco_ck is frequency-divided by a frequency divider 8, and inputted to the phase frequency comparator 1 as the feedback signal fb_ck. A frequency division ratio of the frequency divider 8 is periodically switched between predetermined integers N and N+1 according to a count value of an accumulator 9 that counts the input clock signal comp_ck. The fractional PLL circuit performs negative feedback control such that a frequency and a phase of the feedback signal fb_ck correspond to a frequency and a phase of the input clock signal comp_ck. Additionally, by switching the frequency division ratio of the frequency divider 8, an averaged frequency division ratio as a decimal fraction between N and N+1 is achieved.
In the fractional PLL circuit that changes a frequency division ratio of the frequency divider 8, a phase mismatch occurs in the phase frequency comparator 1 when changing the frequency division ratio. Due to the phase mismatch, a spurious signal is mixed in the output clock signal vco_ck of the voltage-controlled oscillator 4, and a jitter characteristic of the output clock signal vco_ck deteriorates.
Additionally, in the fractional PLL circuit according to the conventional technique, in order to perform fine frequency dividing, it is necessary to increase a frequency division ratio N of the frequency divider 8, and it is not possible to increase a frequency of a signal inputted to the phase frequency comparator 1. Therefore, it is not possible to broaden a loop bandwidth of the fractional PLL circuit, phase noise of the voltage-controlled oscillator 4 increases, and the jitter characteristic deteriorates.